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555 timer calculator (astable and monostable)

Frequency, high time, low time and duty cycle of a 555 astable oscillator from R1, R2 and C; the R1 and R2 for a frequency and duty cycle you want; and the pulse width of a 555 one-shot. Results update as you type.

Indicative calculation; verify before use.

Astable: frequency and duty cycle from R1, R2 and C

Ω
Ω
F

Use a prefix: p, n, u or µ, m, k, M (4k7 = 4.7 kΩ, 100n = 100 nF, 4u7 = 4.7 µF). m is milli, M is mega.

Keep the frequency at 100 kHz or below: TI's NE555 datasheet (SLFS022, section 6.3.2) recommends this to reduce distortion (datasheet).

Frequency
–
Duty cycle (output high)
–

Astable: R1 and R2 for a frequency and duty cycle

Hz
%
F

R1R2FrequencyDuty

In this circuit the duty cycle is always above 50 %, because C charges through R1 + R2 but discharges through R2 only. The E24 row rounds each resistor to the nearest E24 value and shows what you then get; the tolerance of the capacitor and resistors comes on top.

Monostable: pulse width t = 1.1 R C

Ω
F
s

Pulse width
–
R for the wanted width (with this C)
–

How it works

Astable (TI SLFS022, 6.3.2) high time tH = 0.693 (R1 + R2) C low time tL = 0.693 R2 C period T = tH + tL = 0.693 (R1 + 2 R2) C frequency f = 1 / T ≈ 1.44 / ((R1 + 2 R2) C) duty cycle D = tH / T = (R1 + R2) / (R1 + 2 R2) Inverse (choose f, D and C) R2 = (1 − D) / (0.693 f C) R1 = (2 D − 1) / (0.693 f C) Monostable (TI SLFS022, 6.3.1) pulse width tw = 1.1 R C 0.693 = ln 2, 1.44 ≈ 1 / ln 2

In astable mode the capacitor charges through R1 and R2 from 1/3 to 2/3 of the supply, and the output is high; then the discharge pin pulls it back down through R2 alone, and the output is low. Each half takes ln 2 ≈ 0.693 time constants, which is where the factor comes from. R1 (TI calls it RA) runs from VCC to the discharge pin, R2 (RB) from the discharge pin to threshold and trigger. In monostable mode a trigger starts one output pulse that lasts until C has charged through R to 2/3 of the supply: ln 3 ≈ 1.1 time constants.

Worked example (astable): R1 = 1 kΩ, R2 = 10 kΩ, C = 10 nF: tH = 0.693 × 11 000 × 10 nF = 76.2 µs, tL = 0.693 × 10 000 × 10 nF = 69.3 µs, so f = 1 / 145.6 µs = 6.87 kHz with a duty cycle of 11 / 21 = 52.4 %.

Worked example (design): 1 kHz at 60 % duty with C = 100 nF: R2 = 0.4 / (0.693 × 1000 × 100 nF) = 5.771 kΩ and R1 = 0.2 / (0.693 × 1000 × 100 nF) = 2.885 kΩ. With the nearest E24 values, 3.0 kΩ and 5.6 kΩ, you get 1.016 kHz at 60.6 %.

Worked example (monostable): R = 100 kΩ and C = 10 µF give tw = 1.1 × 100 000 × 10 µF = 1.1 s.

The formulas give the nominal timing. The real part also depends on the tolerance of R and C, the capacitor's leakage, and the device's own timing error and drift, which the datasheet lists in its electrical characteristics. CMOS versions (such as TLC555) have their own datasheets; check the formulas there.

Sources (checked 2026-11-03):